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Analog IC co-design for latch-up compliance - EDN Asia
What is Latch-Up and How to Test It - AnySilicon
Latch-up issue in CMOS Logic | Latch-up effect in VLSI - Team VLSI
Analog IC co-design for latch-up compliance - EDN Asia
PPT - Latch-UP PowerPoint Presentation, free download - ID:5779057
LATCH-UP IN CMOS CIRCUITS - YouTube
[SOLVED] - How to use SCR as a Latch? | Forum for Electronics
EEVblog #16 - CMOS SCR Latchup Tutorial - YouTube